Phil
Welcome to Board Talk. This is Jim Hall and Phil Zarrow, the Assembly Brothers, also known as ITM Consulting, here to talk about SMT assembly process problems, solutions, and predicaments.

Jim
Today's question comes from RM, and it's about de-paneling. The question, "Is it acceptable to hand break when de-panelizing our circuit boards. The boards contain QFN and SMD components? Are there any resources or papers that quantify the type of failures caused by hand breaking and stress?"

Phil
I have to say that is something we've encountered quite a bit in our consulting time. We've come across all types of de-paneling methods, and methods to avoid. I would have to say that, in our experience, hand breaking is about the worst method we've seen.

This calls to mind the experience I had a number of years ago. We had a client, an American company, building satellite down-converters. The boards were being built for them in Taiwan. They were having a capacitor-cracking problem. This pre-dates the days of common use of QFNs.

They sent me some photographs and also some cross sectioning. Looking at the crack, it wasn't a thermal crack. It wasn't the wave solder or the re-flow process, which they originally thought, "Maybe it's dwelling on the wave too long," or something along those lines.

It was definitely a mechanical crack, so I said, "Can you send me more slides of your process?" And all of a sudden, there was one where a guy is holding the board, it was a four-up, and he was doing a karate chop to break it apart.

It wasn't a good thing for the boards. So it was, "Here's the problem." Common sense will tell you you're putting undue stress on a board, breaking them that way, even if you've scored the boards properly.

The IPC spec, if I recall, in "Best Practices," is about a third down from each side. You're inducing stress. Most of the pizza cutter manufacturers recommend a keep-away distance from scored area of at least five millimeters. And there, addressing specifically capacitors, but the same thing goes with regard to any kind of device, especially something as tender, and vulnerable, if you will, as a QFN, or even an area aray.

Our good friend, Doctor Zapfart, did an article in "Circuits Assembly," I think it was about three years ago. He was talking about different methodologies that people use de-paneling boards.

He specifically talks about the stress of hand breaking. He also talks about people using paper cutters and makes a derisive comment that you shouldn't go to Wal-Mart for your PC board equipment.

Jim
As Phil said, most of the issues we see are with cracked chip components, resistors and capacitors too close to the breaking zone because of localized flexing. Certainly we're concerned with QFNs, having the weakest, least robust solder joints of any of the IC configurations.

I saw a presentation at a local SMTA chapter meeting, in Boston. It was by DFR Solutions, and they showed pictures of horizontally cracked joints in QFN components due to flexing of the board. I don't recall that they were specific about whether it was de-panelization, but we know that de-panelization can be one of the biggest sources of flexing in the assembly process.

Phil
So there you go, hopefully that answers your question.

Jim
In the meantime, whatever you do, do not solder like my brother.

Phil
And don't solder like my brother.

Jim
And keep the kids away from the flux pot.