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February 22, 2012
New Technologies for Ultra Thin Chips
Program: Materials Tech
From the Single Chip to Wafer Integration
Program: Materials Tech
Memory Minaturazation to Extend Moore's Law
Program: Technology Briefing
Challenges of Package on Package Devices
Program: Materials Tech
Gold Stud Bump Flip Chip Attachment
Program: Materials Tech
Embedded Packaging Technologies
Program: Materials Tech
Evaluation of POP Assembly Under Load
Program: Production Floor
PCB Assembly for 3D Package-on-Package
Program: Production Floor
Design for Flip-Chip and Chip-Size Technology
Program: Materials Tech
Solder Bumping for Flip Chip Technology
Program: Materials Tech
Advances in Graphene Transistors
Program: Technology Briefing
Assembly of Fine Pitch PoP Components
Program: Production Floor
The Huge Potential of Micro-Sensors
Program: Technology Briefing
Breakthrough at the Nanoscale
Program: Technology Briefing
Breakthrough - Ultra Low Power Digital Memory
Program: Technology Briefing
Update - The Revolution in MEMS
Program: Technology Briefing
Science Closer to Ultra-fast Quantum Computer
Program: Technology Briefing
New Method for Prototyping Nanoscale Devices
Program: Technology Briefing
Using Light in New Computer Chip
Program: Technology Briefing
Advances in Computer Chip Core Technology
Program: Technology Briefing
The Latest in Cheap Micro-Surgical Cameras
Program: Technology Briefing
Glob-top Adhesives: A Brief Overview
Program: Production Floor
Dispensing Underfill Can Be Tricky Business
Program: Production Floor
When Should You Use Underfill?
Program: Board Talk
Racetrack Memory - 100,000 Times Faster
Program: Technology Briefing
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These programs cover flip-chip, chip scale packaging, MEMS, semiconductors and more.
New Technologies for Ultra Thin Chips
Paper shows different approaches to use ultra-thin chips for new packages with high density and improved performance.
Program: Materials Tech
From the Single Chip to Wafer Integration
The objective of this paper is to identify the various technological concepts and to give a focus on Chip in Wafer in Silicon technology.
Program: Materials Tech
Memory Minaturazation to Extend Moore's Law
Scientists may have devised an answer for memory miniaturization that adapts to nano manufacturing.
Program: Technology Briefing
Challenges of Package on Package Devices
Paper outlines the process associated with soldering stacked packages using dip flux and dip solder paste designed to overcome the incidence of package warp.
Program: Materials Tech
Gold Stud Bump Flip Chip Attachment
Flip chip bonding is a desirable attachment approach for minimizing size. This paper compares immersion and auto catalytic gold plating processes for flip chip bonding.
Program: Materials Tech
Embedded Packaging Technologies
Paper covers the design, packaging processes, and technology demonstrations of prototypes packaged using embedded technology.
Program: Materials Tech
Evaluation of POP Assembly Under Load
Study evaluates one pass and two pass techniques for assembly of POP devices under torsion loading to compare impact on the fatigue durability.
Program: Production Floor
PCB Assembly for 3D Package-on-Package
Paper focuses on PoP standards, substrate design and assembly methodology for in-line processing of vertically stacked IC package elements.
Program: Production Floor
Design for Flip-Chip and Chip-Size Technology
This paper provides a comparison of flip-chip and wafer level array package methodologies detailed in IPC-7094.
Program: Materials Tech
Solder Bumping for Flip Chip Technology
Paper presents new cost-efficient solder bumping and adapted assembly technologies for processing flip-chips.
Program: Materials Tech
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